1. Field of the Invention
The present invention relates to a stacked memory having a memory core chip, and particularly relates to a stacked memory configured to relieve defective memory cells by replacing them with spare memory cells by using fuses.
2. Description of Related Art
Generally, a memory chip such as a DRAM (Dynamic Random Access Memory) employs a structure in which defective memory cells generated in a memory cell array are replaced with spare memory cells and are relieved thereby. Therefore, a large number of fuse elements are mounted on the memory chip, and the control is performed based on an electrical cut state of each fuse element when a defective memory cell is replaced with a spare memory cell. The fuse elements are generally disposed in an area where no memory cell array is disposed on the memory chip. The above-mentioned memory chip formed by stacking memory chips employs the same technique. Further, through electrodes for signal transmission and power supply connection need to be formed in the stacked memory.
A planar structure of a memory core chip stacked in the stacked memory will be described using FIGS. 12A and 12B. For comparison, FIG. 12A shows a planar structure of a general DRAM chip Ca. The DRAM chip Ca in FIG. 12A has a memory cell array area Ra including a large number of memory cells, a fuse area Rb where a large number of fuses are formed, and a test pad area Rc where a large number of test pads used in a test of the DRAM chip Ca are formed. On the other hand, FIG. 12B shows a planar structure of a memory core chip Cb which is a redesign of the DRAM chip Ca of FIG. 12A specifically for the stacked memory. The memory core chip Cb of FIG. 12B has a through electrode area Rd where the above through electrodes are formed, in addition to the memory cell array area Ra, the fuse area Rb and the test pad area Rc as in FIG. 12A.
Further, FIGS. 13A to 13D show a structure of the stacked memory in which the memory core chips shown in FIGS. 12A and 12B are stacked. As shown in FIG. 13A, a memory core wafer W in which a plurality of memory core chips C are formed is prepared, and there are formed circuit portions 10 including fuses, circuit elements, metal wiring and the like, and through electrodes 11, on the memory core wafer W. Then, after electrodes 12 for external connection is formed on the memory core wafer W as shown in FIG. 13B, the memory core wafer W is diced and the respective memory core chips C are separated as shown in FIG. 13C. Thereafter, stacking process of the memory core chips C is performed as shown in FIG. 13D, electrodes 12 of the memory core chips C are connected to each other so as to function as chip-to-chip connection portions 13, and the stacked memory is completed by mounting an interposer chip IC of the lowermost layer.
The conventional memory core chip Cb of FIG. 12B needs an extra space corresponding to the through electrode area Rd in comparison with the general DRAM chip Ca, as shown with a dotted line in FIG. 12A. Thereby, there arises a problem of an increase in chip size of the memory core chip Cb of the stacked memory in comparison with the general DRAM chip Ca.
Further, a structure has been proposed in which a fuse unit is mounted on a chip different from the memory core chip for the purpose of decreasing the chip size (for example, see Laid-open Japanese Patent Publication No. 2004-119458). However, in such a structure, a large number of chip-to-chip connection signals are required between the chip on which the fuse unit is mounted and the memory core chip, and there arises a problem of an increase in area for forming the through electrodes penetrating the respective chips. This problem becomes pronounced when the capacity of the memory core chip is larger and sufficient redundancy cell control is implemented.
Furthermore, in a manufacturing process of the conventional stacked memory, fuse trimming for replacing defective memory cells with spare memory cells is performed after a wafer test. Then, stacking process of the chips is performed after dicing the chips of the stacked memory. In this case, if a defective memory cell is generated in the stacking process, the fuse trimming has been already completed, so that a problem arises in that the replacement with the spare memory cell cannot be performed at this point.